1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor memory device having an open bit line structure and a refresh operating method thereof.
2. Description of the Related Art
A semiconductor memory device, such as a double data rate synchronous dynamic random access memory (DDR SDRAM), generally has a memory bank for storing data. The memory bank is a group of unit memory cells, each of which is a basic unit for storing data. The unit memory cell is categorized into various types, e.g., 8F2 and 6F2, depending on circuit designs, which determine arrangement of bit lines. The unit memory cell of the type 8F2 has a folded bit line structure, and the unit memory cell of the type 6F2 has an open bit line structure.
In the folded bit line structure, driving bit fines for driving data, for example, positive bit lines, and reference bit lines for comparing data, for example, negative bit lines, are arranged in a memory mat with reference to a sense and amplification unit disposed to sense and amplify the data in a memory area of the semiconductor memory device. In the open bit line structure, the positive bit lines and the negative bit lines are arranged in different memory mats. The memory mat is a unit of predetermined size divided from the memory bank. The memory bank has a plurality of memory mats.
The merits and demerits of the folded bit line structure and the open bit line structure are as follows.
As described above, as to the folded bit line structure, the positive bit lines and the negative bit lines are arranged in the same memory mat, and therefore the same noise may be present on both of the positive and negative bit lines. The noise on both of the positive and negative bit lines cancel each other out, thereby securing stable operations against the noise. As to the open bit line structure, the positive bit lines and the negative bit lines are arranged in different memory mats, and therefore there may be a difference in the noise between the positive and negative bit lines, which makes the open bit line more vulnerable to noise than the folded bit line structure.
As described above, the unit memory cell of the type 8F2 has a folded bit line structure, and the unit memory cell of the type 6F2 has an open bit line structure, which means that the memory bank having the open bit line structure may be designed smaller than the memory bank having the folded bit line structure in view of the same storage capacity. In other words, there is a physical space advantage in using the open bit line structure.
Semiconductor memory devices have lots of unit memory cells, the number of which is increasing as device process technology develops and integration degree increases. When even one of the lots of unit memory cells fails, the semiconductor memory device cannot perform an operation as commanded, and thus the semiconductor memory device should be discarded. However, nowadays, failures statistically occur on only a few unit memory cells, due to increased process technology, and thus it is very inefficient to discard semiconductor memory devices because of a failure on only a few unit memory cells when considering the overall product yield. For this reason, semiconductor memory devices have redundancy memory cells as well as normal memory cells.
When normal memory cells fail, redundancy memory cells replace the failed normal memory cells, which are referred to as repair target memory cells. When the semiconductor memory device is requested to access the repair target memory cell for a read or write operation (from an external device), a normally functioning memory cell is internally accessed instead of the repair target memory cell, and the memory cell replacing the repair target memory cell is a redundancy memory cell. Therefore, when the semiconductor memory device receives an address for the repair target memory cell from an external device, the semiconductor memory device secures errorless operation through a repair operation in which the redundancy memory cell is accessed instead of the repair target memory cell.
FIG. 1 is a schematic diagram illustrating a typical semiconductor memory device. For a simple description, FIG. 1 shows the semiconductor memory device having the open bit line structure, and having 32 memory mats in the memory bank.
Referring to FIG. 1, the semiconductor memory device includes 1st to 32nd memory mats MAT1 to MAT32, and a dummy memory mat MAT_DM. In general, there is a sense and amplification circuit between the memory mats. During the read operation, when word lines of a memory mat are activated, data of the activated memory mat is transferred to and amplified by a sense and amplification circuit corresponding to the memory mat. For example, when word lines of the 2nd memory mat MAT2 are activated, data corresponding to the word lines of the 2nd memory mat MAT2 is transferred to the sense and amplification circuits disposed between the 1st and 2nd memory mats MAT1 and MAT2, and between the 2nd and 3rd memory mats MAT2 and MAT3.
In the memory bank of the semiconductor memory device having the folded bit line structure, a single word line is activated during the read or write operation. As described above, in the memory bank of the semiconductor memory device having the open bit line structure, a single word line is activated during the read or write operation, which is similar to the semiconductor memory device having the folded bit line structure. However, a pair of word lines may be activated in the semiconductor memory device having the open bit line structure due to the following reason.
The memory mat of the semiconductor memory device having the open bit line structure has bit lines coupled to an upper sense and amplification circuit, which is disposed in the upper side of the memory mat, and bit lines coupled to a lower sense and amplification circuit, which is disposed in the lower side of the memory mat. Therefore, during an active operation preceding the read and write operations, when a single word line of the memory mat is activated, corresponding data is transferred to both of the upper and lower sense and amplification circuits.
However, the memory mat disposed near the border of the memory bank, for example, the 32nd memory mat MAT32, does not have the lower sense and amplification circuit, and therefore has half the bit lines activated during the active operation compared to the other memory mats, or the 1st to 31st memory mats MAT1 to MAT31. Therefore, the 32nd memory mat MAT32 should perform operations for the other half of the bit lines of the 1st to 31st memory mats MAT1 to MAT31 in order to keep step with the operations of the 1st to 31st memory mats MAT1 to MAT31.
To this end, the semiconductor memory device having the open bit line structure controls the word lines of the dummy memory mat MAT_DM to be activated at the same time when the word lines of the 32nd memory mat MAT 32 are activated. In other words, the word lines of both of the 32nd memory mat MAT32 and the dummy memory mat MAT_DM are activated at the same time for the activation of the 32nd memory mat MAT32.
As described above, the memory bank of the semiconductor memory device having the open bit line structure has redundancy word lines. For example, the redundancy word lines RED are disposed in each of the 1st, 9th, 17th, and 25th memory mats MAT1, MAT9, MAT17, and MAT25 of the semiconductor memory device shown in FIG. 1.
FIG. 2 is a schematic diagram illustrating a repair operation of the semiconductor memory device shown in FIG. 1. For a simple description, the repair target memory cell in the 8th memory mat MAT8 and the repair target memory cell is repaired by the plurality of redundancy word lines RED of the 1st memory mat MAT1.
In this example, when the semiconductor memory device accesses a word line WL_TT corresponding to the repair target memory cell, which is referred to as a repair target word line, one WL_RED of the plurality of redundancy word lines RED is activated instead of the repair target word line WL_TT.
FIG. 3 is a schematic diagram illustrating a refresh operation of the semiconductor memory device shown in FIG. 1. For a simple description, the refresh operation is performed once per eight memory mats. For reference, the refresh operation is accompanied by the active operation, during which the word lines are activated.
The refresh operations for the 1st, 9th, 17th, and 25th memory mats MAT1, MAT9, MAT17, and MAT25 are performed at the same time. And then, the refresh operations for the 2nd, 10th, 18th and 26th memory mats MAT2, MAT10, MAT18, and MAT26 are performed at the same time. The refresh operations for the group of memory mats are sequentially performed to the 8th, 16th 24th and 32nd memory mats MAT8, MAT16, MAT24, and MAT32. When the refresh operations for the 8th, 16th, 24th, and 32nd memory mats MAT8, MAT16, MAT24, and MAT32 are performed, word lines WL_REF of the dummy memory mat MAT_DM as well as the 8th, 16th 24th, and 32nd memory mats MAT8, MAT16, MAT24, and MAT32 are activated. In other words, during the refresh operations for the 8th, 16th, 24th, and 32nd memory mats MAT8, MAT16, MAT24, and MAT32, there are five (5) activated word lines WL_REF.
FIG. 4 is a schematic diagram illustrating a problem with the semiconductor memory device shown in FIG. 1. For a simple description, the semiconductor memory device shown in FIG. 4 has been repaired as described with reference to FIG. 2, and performs the refresh operations as described with reference to FIG. 3.
Referring to FIG. 4, the semiconductor memory device performs the refresh operations for the 8th, 16th, 24th, and 32nd memory mats MAT8, MAT16, MAT24, and MAT32 as well as the dummy memory mats MAT_DM at the same time. In other words, the word lines WL_REF of the 8th, 16th, 24th, and 32nd memory mats MAT8, MAT16, MAT24, and MAT32 as well as the dummy memory mat MAT_DM are activated. When the word line WL_REF of the 8th memory mat MAT8 is the repair target word line WL_TT corresponding to the repair target memory cell, the redundancy word line WL_RED of the 1st memory mat MAT1 is activated instead of the repair target word line WL_TT of the 8th memory mat MAT8. In other words, during the refresh operations for the 16th, 24th, and 32nd memory mats MAT16, MAT24, and MAT32 as well as the dummy memory mat MAT_DM, the word lines WL_REF of the 16th 24th, and 32nd memory mats MAT16, MAT24, and MAT32 as well as the dummy memory mat MAT_DM are activated, and the redundancy word line WL_RED of the 1st memory mat MAT1 is activated as the repair operation for the repair target word line WL_TT of the 8th memory mat MAT8.
As described above, the dummy memory mat MAT_DM uses the lower sense and amplification circuit, and the 1st memory mat MAT1 uses the upper sense and amplification circuit. In other words, a situation may come in which the dummy memory mat MAT_DM and the 1st memory mat MAT1 uses the same sense and amplification circuit at the same time. In this situation, there is data collision between the dummy memory mat MAT_DM and the 1st memory mat MAT. The data collision may disturb the stable refresh operation of the semiconductor memory device. To sum up, the semiconductor memory device may malfunction when performing the refresh operation after the repair operation.